1. Technical Field
The present invention relates to programmable logic arrays (PLAs) in general, and, in particular, to PLAs used a speed-critical digital system. Still more particularly, the present invention relates to a PLA latch.
2. Description of Related Art
Programmable Logic Arrays (PLAs) are widely used in digital systems to provide programmable logic functions at a relatively low cost. In addition to various control functions, a conventional two-level PLA typically includes two separate logic arrays.
Referring now to the drawings and in particular to FIG. 1, there is illustrated a block diagram of a two-level PLA, according to the prior art. As shown, a two-level PLA 10 includes a first logic array 11, a second logic array 12, an input latch 13 and an output latch 14. First logic array 11 may include, for example, an array of AND functions. Second logic array 12 may include, for example, an array of OR functions.
Accesses to two-level PLA 10 requires several steps. First, input data are latched in input latch 13 before sending to first logic array 11. Next, first logic array 11 is instructed to process the input data, and second logic array 12 is similarly instructed to process the outputs of first logic array 11. Finally, output data are latched in output latch 14 to indicate that the output of two-level PLA 10 now has valid data.
Access speeds to two-level PLA 10 are mainly affected by two parameters. The first parameter, which is known as the access time, describes the time between the requested access to two-level PLA 10 and the output of valid data. The access time of two-level PLA 10 is typically one cycle. The second parameter, which is known as the response time, describes the time for the outputs to reflect as the state of the inputs as soon as possible.
The present disclosure provides architectural improvements to two-level PLA 10 in order to reduce access time and/or response time.